PMC

(a) 32-bit QDI BCLA, and (b) 32-bit QDI BCLARC. The architectures remain the same for RTZ and RTO handshaking. The critical paths traversed for the application of data and spacer also remain the same for RTZ and RTO handshaking. One non-redundant lookahead carry output is produced by each 4-bit QDI BCLG in (a), whereas a non-redundant lookahead carry output and a redundant lookahead carry output is produced by each 4-bit QDI BCLGRC in (b). FA refers to the full adder and XOR3 refers to the 3-input XOR function, and both these belong to (QDI) early output type.

The addition table for bits and its implementation with logic gates. Note that the sum of 1 and 1 (lower right cell in table) is 0 + a carry bit. The carry bit must be added to the sum of the next most significant pair of bits. Thus, summing must proceed sequentially from right to left (from the least significant pair of bits to the most significant pair). If both the addend and the augend are 1 and there is no carry bit in the input, then when this pair are summed, the logic gates generate a ‘0’ for the sum bit and a ‘1’ for the carry bit, the bit that must be fed into the logic gates that operate on the next most significant pair of bits. The generation of the carry bit proceeds via the lowest branch on the logic gate diagram. The generation of the ‘0’ for the sum bit proceeds via the uppermost branch. The topmost XOR gate produces a ‘1’ only if either the addend or the augend is ‘1’, but not both. Thus, when they both are ‘1’ or they both are ‘0’, its output is ‘0’. If the input carry bit is also ‘0’, then so is the sum bit, which is generated by the second or lower XOR gate. If one of the addend and augend bits is ‘1’ but not both, then the output of the top XOR gate is ‘1’. If the input carry bit is ‘0’, then the second (lower) XOR gate generates a ‘0’ for the sum bit. If, however, the input carry bit is ‘1’, then it generates a ‘0’ for the sum bit. Thus, this arrangement of logic gates generates the binary addition table shown at upper right. Conceptually, addition seems about as simple as it gets, but building a machine that implements it noiselessly is not so simple.

Unfolded LSTM network. Three time steps of LSTM are unfolded. In each step, LSTM receives a new input, last output and last carry and generates the next output and the next carry

Deterministic simulation of the ripple-carry adder circuit responding to various inputs. We plot the output species from each section of the pipeline used to coordinate the output from each adder. The carry-bit output from each adder is represented by and . The output of the C-element () arrives strictly before the output from the adder. The logical input for a is 1 and 0 for the first adder, 1 and 0 for the second adder, and 1 and 0 for the third adder. In b we show the computation on different inputs, namely 1 and 0 for the first adder, 0 and 0 for the second adder, and 1 and 0 for the third adder. The crossover in the concentrations of output species of the C-element and the logical output of 1 (resulting from inputs 0, 1 and carry of 1) in the third adder (plots and ) indicates faster convergence but does not affect the results in further stages of the pipeline